1. Field of the Invention
The present invention relates to an image processing apparatus including a pixel data storage means for storing pixel data representing pixels in a screen and, more particularly, to an image processing apparatus including an image data storage device for storing pixel data to be used in an image decoding process.
2. Description of the Background Art
Efforts have been made to make international standards for the compression and expansion of image data by International Organization for Standardization (ISO), International Telegraph and Telephone Consultative Committee (CCITT, now ITu-T) and international Electric Committee (IEC).
JPEG standard among international standards, made by the joint photographic expert group of ISO and CCITT prescribe an algorithm for the compression and expansion of color still pictures. Meanwhile, MPEG standard is now being drafted by Moving Picture Expert Group of ISO and IEC, and it defines compression and decompression algorithms for color moving images. Further, the H. 261 standard, which is under examination by CCITT, prescribes a compression/expansion algorithm suitable for the video conference system and the visual telephone system.
The JPEG standard, the MPEG standard and the H. 261 standard for an image compressing process include a discrete cosine transformation process, a quantizing process and a Huffman coding process. For example, the JPEG standard for color still picture processing comprises, as basic systems, an adaptive DCT process, a quantizing process and a Huffman coding process. The JPEG standard comprises, as extension systems, an adaptive DCT process, a hierarchical coding process, an arithmetic coding process and an adaptive Huffman coding process. The MPEG standard for moving picture storing process comprises a motion compensation interframe prediction process, a DCT process, a quantizing process and a Huffman coding process. The H. 261 standard for the video conference system and the visual telephone system includes a motion compensation/interframe prediction process, a DCT process, a quantizing process and a Huffman coding process.
Efforts have been made to develop an LSI circuit device for processing images according to those international standards, i.e., an image processing apparatus. A conventional image processing apparatus will be described hereinafter. FIG. 17 is a diagrammatic view of assistance in explaining an operation of the conventional image processing apparatus for addressing a frame buffer memory.
The conventional image processing apparatus is provided with a frame buffer memory to store pixel data to be subjected to the aforesaid processes. The frame buffer memory has thirty-two planes of memory cell arrays. When one row address RA and one column address CA are specified, one bit of data is read from (or written into) each memory cell array. Therefore, when one row address RA and one column address CA are specified, thirty-two bits of data are read from the memory cell arrays. Generally, one pixel is represented by eight bits of data. Therefore, thirty-two bits of data are able to represent four pixels; that is, four pixel data representing four pixels can be handled by specifying one row address RA and one column address CA.
A procedure for addressing the frame buffer memory will be described hereinafter. In FIG. 17, pixel data of sixteen pixels in a column and eight pixels in a row are stored in the frame buffer memory in a frame structure and in data blocks each of four pixels in a column. Referring to FIG. 17, pixel data TFP0 and TFP1 of a top field, and pixel data BFP0 and BFP1 of a bottom field are stored alternately in each of data blocks D0 to D31. Thus, the top field pixel data TFP and the bottom field pixel data BFP are stored in alternate rows, respectively, in the data blocks D0 to D31. The top field pixel data and the bottom field pixel data represents the pixel data of a frame.
One row address and one column address are assigned to each of the data blocks D0 to D31. For example, a row address RA0 and a column address CA0 are assigned to the data block D0. Therefore, when the row address RA0 and the column address CA0 are specified, four pixel data stored in the data block D0 of the frame buffer memory are read or four pixel data are written into the data block D0.
When storing pixel data in the frame buffer memory by the foregoing procedure, the pixel data are transferred by the following procedure First, if frame structure pixel data of eight pixels in a column and eight pixels in a row is necessary when transferring frame structure pixel data, pixel data stored, for example, in the data blocks D0 to D15 are transferred. In this case, since the top field pixel data and the bottom field pixel data are stored in each of the data blocks D0 to D15, only the necessary pixel data can be transferred. On the other hand, if field structure pixel data of, for example, eight pixels in a column and eight pixels in a row is necessary when transferring field structure pixel data, pixel data stored in the data block D0 to D31 must be transferred. Although the field structure pixel data needs only either the pixel data of the top field or the pixel data of the bottom field, unnecessary pixel data needs to be transferred because two pixel data for each of the top field and the bottom field are stored in each data block. Therefore, when transferring field structure pixel data, a quantity of pixel data twice that of necessary pixel data are transferred.
The conventional image processing apparatus needs to transfer a quantity of pixel data twice that of necessary pixel data when transferring field structure pixel data and hence the image processing apparatus is unable to transfer the pixel data at a high data transfer rate. Since the buffer memory to which the pixel data are transferred must store a quantity of pixel data twice that of the necessary pixel data, the buffer memory must have a large storage capacity twice an actually necessary storage capacity.
Furthermore, when writing data at a plurality of different addresses, a plurality of precharging cycles of precharging period is necessary, which requires a long time for transferring data.